datasheet loco? pll cloc k multiplier ics502 idt? / ics? loco? pll clock multiplier 1 ics502 rev m 051310 description the ics502 loco tm is the most cost effective way to generate a high-quality, high-frequency clock output and a reference from a lower frequency crystal or clock input. the name loco stands for low co st oscillator, as it is designed to replace crystal osc illators in most electronic systems. using phase-locked loop (pll) techniques, the device uses a standard fundamental mode, inexpensive crystal to produce output clocks up to 160 mhz. stored in the chip?s rom is the ability to generate six different multiplication factors, allowing one chip to output many common frequencies (see table on page 2). this product is intended for clock generation. it has low output jitter (variation in the output period), but input to output skew and jitter are not defined or guaranteed. for applications which require defined input to output skew, use the ics570b. features ? packaged as 8-pin soic or die ? pb (lead) free package ? idt?s lowest cost pll clock ? zero ppm multiplication error ? easy to cascade with ics5xx series ? input crystal frequency of 5 ? 27 mhz ? input clock frequency of 2 ? 50 mhz ? output clock frequencies up to 190 mhz ? low jitter ? 50 ps one sigma ? compatible with all popular cpus ? duty cycle of 45/55 up to 160 mhz ? operating voltages of 3.0 to 5.5 v ? 25 ma drive capability at ttl levels ? industrial temperature version available ? advanced, low-power cmos process block diagram pll clock multiplier circuitry and rom crystal or clock input vdd crystal oscillator s1, s0 x1/iclk x2 2 clk ref gnd
ics502 loco? pll clock multip lier clock multiplier idt? / ics? loco? pll clock multiplier 2 ics502 rev m 051310 pin assignment clock d ecoding table (mhz) minimum input frequency for all selections is per table on page 3. 0 = connect directly to ground 1 = connect directly to vdd m = leave unconnected (floating) common output frequency examples (mhz) pin descriptions x1/iclk vdd gnd s1 ref s0 clk x2 1 2 3 4 8 7 6 5 8 pin (150 mil) soic s1 s0 clk 00 x2 01 x5 m0 x3 m 1 x3.33 10 x4 11 x2.5 output 20 25 30 32 33.33 37.5 40 48 50 54 60 input 10 10 10 16 10 15 20 16 20 13.5 20 selection (s1, s0) 0, 0 1, 1 m, 0 0, 0 m, 1 1, 1 0, 0 m, 0 1, 1 1, 0 m, 0 output 64 66.66 72 75 80 81 90 100 108 120 135 input 16 20 24 15 20 27 27 20 27 24 27 selection (s1, s0) 1, 0 m, 1 m, 0 0, 1 1, 0 m, 0 m, 1 0, 1 1, 0 0, 1 0, 1 pin number pin name pin type pin description 1 xi/iclk input crystal connection or clock input. 2 vdd power connect to +3.3 v or +5 v. 3 gnd power connect to ground. 4 ref output buffered crysta l oscillator output clock. 5 clk output clock output per table above. 6 s0 input select 0 for output clock. connect to gnd or vdd. 7 s1 input select 1 for output clock. connect to gnd or vdd or float. 8 x2 input crystal connection. leave unconnected for clock input.
ics502 loco? pll clock multip lier clock multiplier idt? / ics? loco? pll clock multiplier 3 ics502 rev m 051310 external components decoupling capacitor as with any high-performance mixed-signal ic, the ics502 must be isolated from system power supply noise to perform optimally. a decoupling capacitor of 0.01f must be connected between vdd and gnd. it must be connected close to the ics502 to minimize lead inductance. no external power supply filtering is r equired for the ics502. series termination resistor a 33 ? terminating resistor can be used next to the clk pin. the total on-chip capacitance is approximately 12 pf. a parallel resonant, fundamental mode crystal should be used. crystal load capacitors the device crystal connections should include pads for small capacitors from x1 to ground and from x2 to ground. these capacitors are used to adj ust the stray capacitance of the board to match the nominally required crystal load capacitance. because load capacitance can only be increased in this trimming proc ess, it is important to keep stray capacitance to a minimum by using very short pcb traces (and no vias) between the crystal and device. crystal capacitors, if needed, must be connected from each of the pins x1 and x2 to ground. the value (in pf) of these crystal caps should equal (c l -12 pf)*2. in this equation, c l = crystal load capacitance in pf. example: for a crystal with a 16 pf load capacitance, each crystal capacitor would be 8 pf [(16-12) x 2] = 8. absolute maximum ratings stresses above the ratings listed below can cause perm anent damage to the ics502. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operat ional sections of the specif ications is not implied. exposure to absolute maximum rating conditions for extended periods can affect product re liability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions item rating supply voltage, vdd 7 v all inputs and outputs -0.5 v to vdd+0.5 v ambient operating temperature (industrial) -40 to +85 c ambient operating temperature (commercial) 0 to +70 c storage temperature -65 to +150 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature (commercial) 0 ? +70 c ambient operating temperature (industrial) -40 ? +85 c power supply voltage (measured in respect to gnd) +3 +5.5 v
ics502 loco? pll clock multip lier clock multiplier idt? / ics? loco? pll clock multiplier 4 ics502 rev m 051310 dc electrical characteristics vdd=5.0 v 5% , ambient temperature -40 to +85 c, unless stated otherwise parameter symbol conditions min. typ. max. units operating voltage vdd 3 5.5 v input high voltage, iclk only v ih iclk (pin 1) (vdd/2)+1 v input low voltage, iclk only v il iclk (pin 1) (vdd/2)-1 v input high voltage v ih oe (pin 7) 2 v input low voltage v il oe (pin 7) 0.8 v input high voltage v ih s0, s1 vdd-0.5 v input mid voltage v im s1 vdd/2 v input low voltage v il s0, s1 0.5 v output high voltage v oh i oh = -25 ma 2.4 v output low voltage v ol i ol = 25 ma 0.4 v idd operating supply current, 20 mhz crystal no load, 100 mhz 20 ma short circuit current clk output + 70 ma on-chip pull-up resistor pin 7 270 k ? input capacitance, s1, s0, and oe pins 4, 6, 7 4 pf
ics502 loco? pll clock multip lier clock multiplier idt? / ics? loco? pll clock multiplier 5 ics502 rev m 051310 ac electrical characteristics vdd = 5.0 v 5% , ambient temperature -40 to +85 c, unless stated otherwise parameter symbol conditions min. typ. max. units input frequency, crystal input f in 527mhz input frequency, clock input f in 250mhz output frequency, vdd = 4.5 to 5.5v f out 0 to +70 c 14 160 mhz output frequency, vdd = 3.0 to 3.6v -40 to +85 c 14 120 mhz output frequency, vdd = 4.5 to 5.5v f out +25 c 14 190 mhz output frequency, vdd = 3.0 to 3.6v +25 c 14 140 mhz output clock rise time t or 0.8 to 2.0 v 1 ns output clock fall time t of 2.0 to 8.0v 1 ns output clock duty cycle t od 1.5v, up to 160 mhz 45 49-51 55 % pll bandwidth 10 khz output enable time, oe high to output on 50 ns output disable time, oe low to tri-state 50 ns absolute clock period jitter t ja deviation from mean + 70 ps one sigma clock period jitter t js 25 ps
ics502 loco? pll clock multip lier clock multiplier idt? / ics? loco? pll clock multiplier 6 ics502 rev m 051310 package outline and package dimensions (8-pin soic, 150 mil. narrow body) package dimensions are kept current with jedec publication no. 95 ordering information parts that are ordered with an ?lf? suffix to the part number are the pb-free configuration and are rohs compliant. while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any paten ts or other rights of third parties, which would resul t from its use. no other circuits, patents, or licenses are im plied. this product is intended for use in normal commercial applications. any other applications such as those requiring extended temperature range, high reliab ility, or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves th e right to change any circuitry or specifications without noti ce. idt does not authorize or warrant any idt product for use in life support devices or critical medical instruments. part / order number marking shipping packaging package temperature 502mlf 502mlf tubes 8-pin soic 0 to +70 c 502mlft 502mlf tape and reel 8-pin soic 0 to +70 c 502milf 502milf tubes 8-pin soic -40 to +85 c 502milft 502milf tape and reel 8-pin soic -40 to +85 c 502-dwf - die on uncut, probed wafers 0 to +70 c 502-dpk - tested die in waffle pack 0 to +70 c d eh c h x 45 0 b e q a pin 1 index area millimeters inches symbol min max min max a 1.35 1.75 0.0532 0.0688 a1 1.10 0.25 0.0040 0.0098 b 0.33 0.51 0.013 0.020 c 0.19 0.25 0.0075 0.0098 d 4.80 5.00 .1890 .1968 e 3.80 4.00 0.1497 0.1574 e 1.27 basic 0.050 basic h 5.80 6.20 0.2284 0.2440 h 0.25 0.50 0.010 0.020 l 0.40 1.27 0.016 0.050 a0 8 0 8
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